Welcome to Sintel’s documentation!¶
Copyright (c) 2019 Wilfer Daniel Ciro Maya <firstname.lastname@example.org>, Director Luis Miguel Capacho <email@example.com>. Degree work for Universidad del Quindío, Colombia.
Sintel is a simulator and modeler of basic digital systems that allows, in addition to visualizing inputs and outputs in real time, to export the model to a hardware description language such as VHDL and verilog.
Sintel is written in python with the QT graphics library, it’s an open source project with GPLv3 license or later.
In this manual we hope to give you a guide to the use and operation of the different parts of the software, as well as to invite you to contribute with various elements within it such as the creation of components.
You can find the master code in this link <https://gitlab.com/WilferCiro/sintel>
- 1. State machine (sm)
- 2. Add and edit components